1. Field of the Invention
The present invention relates to a semiconductor device having a circuit made up by a thin film transistor (hereinafter referred to as TFT) and it's manufacturing method. More particularly, the invention relates to configurations of an electro-optic apparatus typified by a liquid crystal display, and of electronic equipment equipped with an electro-optic apparatus as a component thereof, and to their manufacturing method. Note that a semiconductor device herein means all devices, which can work by utilizing semiconductor characteristics, and the above-described electro-optic apparatus and electronic equipment fall under the category of such devices.
2. Description of the Related Art
In recent years, a thin film transistor (TFT) using a semiconductor thin film (approximately a-few-nm-thick to a-few-hundreds-nm-thick) formed on a substrate having an insulating surface has been constructed, and the development of a semiconductor device having a large area integrated circuit formed using this TFT has been pursued. An active-matrix liquid crystal display and a light emitting device are well known as a representative example of such device. Particularly, a TFT, wherein a crystal silicon film (typically, polycrystalline silicon film) is used as an active region, has a high field effect mobility, so that various functional circuits can be formed using such TFTs.
For example, in an active-matrix liquid crystal display, a pixel circuit for displaying an image for each function block, a shift register circuit built on a CMOS circuit, a level shifter circuit, a buffer circuit, and a drive circuit for controlling a pixel circuit such as a sampling circuit are formed on a single substrate. Additionally, an increase in substrate area is especially an essential element for enhancing a production efficiency. In recent years, the trends in increasing substrate area for improving a production efficiency have been becoming more remarkable, so that it is expected that a substrate having a edge size of more than 1 m will be used in a production plant in the future.
Incidentally, a pixel circuit of an active-matrix liquid crystal display has from tens to millions of pixels, each having a TFT (pixel TFT) arranged therein. Each of the pixel TFTs is provided with a pixel electrode. In the opposite substrate side across a liquid crystal, an opposite electrode is provided to form a kind of capacitor, which uses the liquid crystal as a dielectric substance. A voltage to be applied to each individual pixel is controlled by the switching function of the TFT to control an electric charge to be supplied to this capacitor, whereby driving the liquid crystal to control an amount of transmitted light and to display an image.
A pixel TFT serves as a switching element to apply a voltage to the liquid crystal and to drive it. The liquid crystal is driven with alternating current, so that a system referred to as a frame inverting drive is adopted in many cases. For this system, it is important to comprise pixel TFTs each having a characteristic that an OFF current value (drain current when a TFT is in an OFF state) is sufficiently low, for the purpose of keeping its power consumption low.
As TFT structure for reducing an OFF current value, the LDD (Lightly Doped Drain) structure is known. In this structure, there is provided a region lightly doped with an n-type impurity element or a p-type impurity element between a channel region and a source region or drain region formed by doping an n-type impurity element or p-type impurity element heavily, and this region is referred to as an LDD region. In addition, as means for preventing the deterioration of ON current values due to hot carriers, so-called GOLD (Gate-drain Overlapped LDD) structure is known, in which an LDD region is overlapped with a gate electrode with a gate insulating film interposed therebetween. It is known that this structure can relax a strong electric field in the vicinity of a drain to thereby prevent hot carriers from flowing into a drain and it is useful to prevent the occurrence of deterioration phenomena.
Incidentally, the energy of ions implanted into a semiconductor film in a process for introducing an impurity element is much larger than binding energies of elements making up the semiconductor film. As a result, ions implanted into the semiconductor film flick elements making up the semiconductor film out of the lattice points and cause defects in the crystalline. Therefore, after doping, thermal treatment is often carried out to restore the defects and to activate an implanted impurity element simultaneously. For this thermal treatment, a thermal annealing technique using a furnace annealer is most commonly used. The activation of impurity elements is an important process for making impurity element doped regions low resistance areas and making those regions serve as an LDD region, a source region, and a drain region.
Now, methods for introducing impurity elements include the plasma doping technique, ion doping technique, and ion implantation technique. The plasma doping technique and ion doping technique are methods for introducing ions without mass separation (non-mass separation type methods), and apparatuses for introducing impurity elements using these methods include a plasma doping apparatus and an ion doping apparatus (an ion shower doping apparatus). Further, the ion implantation technique is a method for separating in masses and introducing ions and an apparatus for introducing impurity elements using this method is the ion implanter.
With increasing the size of a substrate, however, the thermal annealing technique, which is carried out using a furnace annealer, is a contributing factor to low throughputs in manufacturing semiconductor devices. To minimize the use of a furnace annealer, a method whereby at least activation of impurity elements after doping is carried out by a laser annealing technique is conducive. However, there has been a problem with the laser annealing activation of impurity elements that electrical characteristics become worse compared with the thermal annealing technique using a furnace annealer.
For example, as for a GOLD structure TFT as shown in FIGS. 1A to 1E, a case where a p-channel TFT is manufactured will be described. A 50 nm-thick silicon nitride oxide film 11a (at a composition ratio of Si=32%, O=27%, N=24%, and H=17%), and then a 100 nm-thick silicon nitride oxide film 11b (at a composition ratio of Si=32%, O=59%, N=7%, and H=2%) are deposited as an underlying insulating layer 11 over a glass substrate 10 by the plasma CVD technique. On the underlying insulating layer 11, a 54 nm-thick amorphous silicon film is formed as a semiconductor film 12 by the plasma CVD technique, followed by forming a 115 nm-thick silicon nitride oxide film (at a composition ratio of Si=32%, O=59%, N=7%, and H=2%) as an insulating film 13 over the semiconductor film 12, and forming a first conductive film 14 and then a second conductive film 15 over the insulating film 13, where the first conductive film 14 and second conductive film 15 are formed as a 50 nm-thick TaN film and as a 370 nm-thick W (tungsten) film using a sputter technique, respectively. (FIG. 1A)
Subsequently, a resist 16a is formed over the second conductive film 15, and etched to form a gate electrode, where the etching is carried out under first and second etching conditions. In either etching condition, an ICP etching technique is used. However, according to the first condition, plasma is created under a pressure of 1 Pa with etching gases of CF4, Cl2, and O2 at a gas flow rate ratio of 25:25:10 (sccm) to perform etching, while a coil electrode is applied with a 500W RF (13.56 MHz) power, and a substrate side (sample stage) is applied with a 20W RF (13.56 MHz) power, thereby to apply a negative self-bias voltage between them substantially. The insulating film 13, the first conductive film 14 and the second conductive film 15 are etched to be shown as reference numerals 19a, 18a and 17a, respectively (FIG. 1B). In the second etching condition, plasma is created under a pressure of 1 Pa with etching gases of CF4 and Cl2 at a gas flow rate ratio of 30:30 (sccm) to perform etching, while the coil electrode is applied with a 500W RF (13.56 MHz) power and the substrate side (sample stage) is applied with a 20W RF (13.56 MHz) power, thereby to apply a negative self-bias voltage between them substantially The resist 16a, the insulating film 19a, the first conductive film 18a and the second conductive film 17a are etched to be shown as reference numerals 16b, 19b, 18b and 17b (FIG. 1C).
In addition, a doping process is performed with B2H6 gas at an acceleration voltage of 60 keV, and a dose of 1.5×1016 atoms/cm2 using an ion doping apparatus, wherein a plasma generating method is of DC (direct current) arc discharge mode. Thus, a source or drain region 22, an LDD region 21 and a channel region 20 are formed (FIG. 1D). The DC arc discharge mode is a method for generating plasma by flowing direct current through a tungsten filament. Now, this method is herein referred to as a DC mode.
Subsequently, the activation of impurity elements is performed in various conditions. With a thermal annealing technique using a furnace annealer, the condition of 550° C. for four hours is adopted; with a laser annealing technique, the activation is performed using second harmonics of a YAG laser in the case of irradiating a top surface of a substrate (a surface where a device is to be formed is herein defined as a “top surface”), and in the case of irradiating a rear surface (a surface opposite from a surface where a device is to be formed is herein defined as a “rear surface”), provided that the activation is performed after the formation of a 50 nm-thick silicon oxide film 23 when carrying out a thermal annealing technique using a furnace annealer. The semiconductor films obtained by performing the different types of activation are used to manufacture TFTs, each having channel region design values of 8 μm both in length and width, and then the electrical characteristics of the resultant TFTs are measured. The results are shown in FIGS. 2A to 2C. FIG. 2A shows a case where a thermal annealing technique using a furnace annealer is used for activation. FIG. 2B shows a case where laser light irradiates the substrate from the top surface thereof. FIG. 2C shows a case where laser light irradiates the substrate from the rear surface.
The TFT of FIG. 2A exhibits a good S value (sub-threshold coefficient: a value of gate voltage required to cause a value of drain current to be changed by one order at logarithm scale), a high mobility and a large ON current value, so that it has characteristics enough to serve as a semiconductor device. The TFT of FIG. 2B, however, exhibits an unfavorable S value, a low ON current value and a low mobility. The TFT of FIG. 2C exhibits a higher mobility than that of FIG. 2B, but it varies widely within the substrate. Thus, when a laser annealing technique performs the activation of impurity elements, the electrical characteristics become worse compared with a thermal annealing technique using a furnace annealer.
Therefore, it is an object of the invention to achieve good electrical characteristics in a GOLD structure TFT. Also, it is another object of the invention to improve the operating characteristics, reliability and yield of a semiconductor device. Further, it is an object of the invention to reduce the manufacturing cost of semiconductor devices.